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Backend-Terminated (BUSY) Cycle during Data Burst (Target)
Figure 6-28 shows BUSY being asserted when RD_SYNC is active. Figure 6-29 on page 78 shows BUSY asserted
during a write cycle. In the case shown, the backend interface had previously indicated that it was ready to accept data by
asserting WR_BE_RDY before asserting BUSY, causing two data words to be written before the PCI cycle was
stopped.
cycle
0
1
2
3
4
5
6
7
8
9
10
clk
framen
cben[3:0]
6
0
ad[31:0]
ADDR
0
1
par
devseln
irdyn
trdyn
stopn
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
busy
error
0
mem_add[15:0]
0000
0004
mem_data_in[31:0]
0
1
rd_sync
Figure 6-28 · Backend Burst Read Cycle Terminated by BUSY (RD_SYNC = 1)
v4.0
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